- 🔭 Computer Engineering Graduate Student focusing on Computer Architecture, FPGA and VLSI
- 📫 How to reach me: Twitter - @vivekmohan27
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RTL_Toolchain
RTL_Toolchain PublicPython toolchain that autogenerates synthesizable Verilog RTL from a JSON ISA specification control unit decoder, ROM based control unit, and testbench for a custom 16-bit processor ISA.
Verilog
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RTL_Post_Processor
RTL_Post_Processor PublicPython tool that automatically detects registers without clock enables in Verilog RTL and inserts latch-based clock gating cells, reduces dynamic power consumption; outputs modified Verilog and JSO…
Python
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Mario-Gram-App
Mario-Gram-App PublicInstagram clone built with React + Firebase + Material-UI
JavaScript 1
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