Chinese-Logic-Group

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1. My_Opensource_AZPR_SOC My_Opensource_AZPR_SOC Public

   根据最近看的一本书编写的对应RTL以及Testbench

   Verilog 20 9

2. video_timing_generator video_timing_generator Public

   标准视频时序生成器

   Verilog 10 3

3. AXI_BFM AXI_BFM Public

   AXI 总线验证 模块

   SystemVerilog 10 3

4. altera_vdma_ddr altera_vdma_ddr Public

   altera video DMA

   Verilog 10 5

5. sort sort Public

   排序 verilog 实现

   Verilog 9 8

6. RGB-YCbCr RGB-YCbCr Public

   RGB 和 YCbCr 高精度互转

   Verilog 7 6